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data sheet ICS854104ag revision a august 14, 2009 1 ?2009 integrated device technology, inc. low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104 general description the ICS854104 is a low skew, high performance 1-to-4 differential-to-lvds clock fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. utilizing low voltage differential signaling (lvds), the ICS854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100 ? . the ICS854104 accepts a differential input level and translates it to lvds output levels. guaranteed output and part-to-part skew characteristics make the ICS854104 ideal for those applications demanding well defined performance and repeatability. features ? four differential lvds output pairs ? one differential clock input pair ? clk/nclk can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? each output has an individual oe control ? maximum output frequency: 700mhz ? translates differential input signals to lvds levels ? additive phase jitter, rms: 0.232ps (typical) ? output skew: 50ps (maximum) ? part-to-part skew: 350ps (maximum) ? propagation delay: 1.3ns (maximum) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 q0 nq0 q1 nq1 q2 nq2 q3 nq3 oe3 nclk clk gnd v dd oe2 oe1 oe0 q0 nq0 q1 nq1 q2 nq2 q3 nq3 clk oe2 oe3 oe1 oe0 nclk pulldown pullup/pulldown pullup pullup pullup pullup pin assignment ICS854104 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view block diagram
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 2 ?2009 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. output enable function table number name type description 1 oe0 input pullup output enable pin for q0, nq0 outputs. see table 3. lvcmos/lvttl interface levels. 2 oe1 input pullup output enable pin for q1, nq1 outputs. see table 3. lvcmos/lvttl interface levels. 3 oe2 input pullup output enable pin for q2, nq2 outputs. see table 3. lvcmos/lvttl interface levels. 4v dd power positive supply pin. 5 gnd power power supply ground. 6 clk input pulldown non-inverting differential clock input. 7 nclk input pullup/pulldown inverting differential clock input. v dd /2 default when left floating. 8 oe3 input pullup output enable pin for q3, nq3 outputs. see table 3. lvcmos/lvttl interface levels. 9, 10 nq3, q3 output differential out put pair. lvds interface levels. 11, 12 nq2, q2 output differential out put pair. lvds interface levels. 13, 14 nq1, q1 output differential out put pair. lvds interface levels. 15, 16 nq0, q0 output differential out put pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? inputs outputs oe[3:0] q[0:3], nq[0:3] 0 high-impedance 1 active (default)
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 3 ?2009 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuos current surge current 10ma 15ma package thermal impedance, ja 100.3c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 75 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd = v in = 3.465v 150 a i il input low current v dd = 3.465v, v in = 0v -5 a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v dd = v in = 3.465v 150 a i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 4 ?2009 integrated device technology, inc. table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 5. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at f max unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential crossing point of the input to the differential output crossing point. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the ou tputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 250 350 450 mv ? v od v od magnitude change 50 mv v os offset voltage 1.2 1.3 1.45 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 0.9 1.3 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz) 0.232 ps tsk (o) output skew; note 2, 4 50 ps tsk (pp) part-to-part skew; note 3, 4 350 ps t r / t f output rise/fall time 20% to 80% 180 660 ps odc output duty cycle 45 55 %
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 5 ?2009 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.232ps (typical) ssb phase noise dbc/hz offset from carr ier frequency (hz)
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 6 ?2009 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit propagation delay output skew differential input level part-to-part skew output duty cycle/pulse width/period scope qx nqx lvds 3.3v5% power supply +? float gnd v dd t pd q[0:3] nq[0:3] nclk clk t sk(o) qx nqx qy nqy v dd nclk clk gnd v cmr cross points v pp t sk(pp) part 1 part 2 qx nqx qy nqy t pw t period t pw t period odc = x 100% q[0:3] nq[0:3]
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 7 ?2009 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time differential output voltage setup offset voltage setup 20% 80% 80% 20% t r t f v od q[0:3] nq[0:3] ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? ? ? v os / ? v os v dd
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 8 ?2009 integrated device technology, inc. application information wiring the differential input to accept single-ended levels figure 1 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 9 ?2009 integrated device technology, inc. differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 2a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 2b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 2f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 10 ?2009 integrated device technology, inc. 3.3v lvds driver termination a general lvds interface is shown in figure 3. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 3. typical lvds driver termination 3.3v lvds driver r1 100 ? ? + 3.3v 50 ? 50 ? 100 ? differential transmission line
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 11 ?2009 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS854104. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854104 is the sum of the core power plus the analog power plus the power dissipated in t he load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.465v * 75ma = 259.875mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. limiting the internal transistor junction temperatur e, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.260w * 100.3c/w = 96.1c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 12 ?2009 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS854104 is: 286 pin compatible with sn65lvds104 package outline and package dimensions package outline - g suffix for 16 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 13 ?2009 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 854104ag 854104ag 16 lead tssop tube 0 c to 70 c 854104agt 854104ag 16 lead tssop 2500 tape & reel 0 c to 70 c 854104aglf 854104al ?lead-free? 16 lead tssop tube 0 c to 70 c 854104aglft 854104al ?lead-free? 16 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ICS854104 data sheet low skew, 1-to-4, differential-to-lvds fanout buffer ICS854104ag revision a august 14, 2009 14 ?2009 integrated device technology, inc. revision history sheet rev table page description of change date a t5 4 ac characteristics - deleted "bank a" test conditions from part-to-part skew row. 8/13/09
ICS854104 datasheet low skew, 1-to-4, differential-to-lvds fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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